MODULE mem68k "R582 "29.12.2017 remove other that v5x pcb "make config pin input "make ram on regardless of autoconfig DECLARATIONS //pcb v58,59 //xc9572xl-vq64, -7 speed grade. global clock and reset. unused pins programmable grounds should not matter, no unused pins. a23..a1 pin 47,46,45,44,43,42,40,39,38,36,35,34,33,32,31,27,25,24,23,20,19,18,17; d15..d12 pin 48,49,50,51; da11..da0 pin 60,59,58,57,56,52,9,8,7,6,5,4; cpu_nreset, cpu_clk, cpu_r_w, cpu_nuds, cpu_nlds, cpu_nas pin 64,16,10,13,15,12; declarations clock = cpu_clk.pin; reset = !cpu_nreset.pin; !bufena pin 11 istype 'com'; !ras, !ucas, !lcas, !ramoe, !ramwr pin 2,62,63,61,1; //config in config_nin pin 22; config_nout node istype 'com';//node only, no output declarations dly_as node istype 'reg'; equations dly_as.aclr = cpu_nas.pin; dly_as.clk = !clock; "falling edge (nas assert 62ns max from clock rise?, negate ?) 7,16 MHz cycle 140ns (/2 =70ns) dly_as := !cpu_nas.pin; declarations "nodes mem_selected node istype 'com'; access_ras, access_cas, mux_switch_column_address node istype 'reg'; rfsh_cas node istype 'reg'; rfsh_ras node istype 'com'; "autoconfig synch0, synch1 node istype 'reg'; autoconfig_started node istype 'reg'; autoconfig_done node istype 'reg'; ah = [a23,a22,a21,a20].pin; "set EQUATIONS "// chip selector decoder "2xxxxx..9xxxxx=> 001x 010x 011x 100x @ifndef fourmeg { mem_selected = (ah==2)#(ah==3)#(ah==4)#(ah==5)#(ah==6)#(ah==7)#(ah==8)#(ah==9); } @ifdef fourmeg { mem_selected = (ah==2)#(ah==3)#(ah==4)#(ah==5); //here it is assumed that autoconfig assigns 4 megs to 2xxxxx..5xxxxx, should be if this is the first mem board in autoconfig chain } "*************************************************** "clock high to state2, as asserted 3-60 nS "clock low to s7, as negated -..62 nS (8MHZ cpu) 3..25(20MHz cpu) "interrupt cycles have high address =111111... when nas, no int cycle at ram addr "*************************************************** "// normal cycle generator "previous clock up, if AS negated, was entering state2 (clock low enters s3). if AS now (rising clock) then asserted, it is state4 "lds,uds assert on _write_ at s4 access_ras.clk = clock; access_ras.aclr = cpu_nas.pin; "as negated -..62 ns after clock fall, asynch. terminates access_ras,cas access_cas.clk = clock; access_cas.aclr = cpu_nas.pin; "access_ras with state4, row address (gated by AS) at dram, at state2 or 3, also r/w low to dram /rw Data set-up time tDS 0 nS Data hold time tDH 10 ns // access_ras := !dly_nas.pin & mem_selected ; "glitch from invalid address bus? address strobe should gate it off? // dly_as vs. !cpu_nas.pin: clock rise to cpu_nas 3-62ns? access_ras := dly_as.fb & mem_selected; access_cas := access_ras.fb; "goes '1' at next clock after access_ras state 6. Column address at dram after entering s5 by cpu clock going low) "read data from dram latched to 68000 entering state7 clock fall (70ns, tcac=20ns) "write data from 68000 removed at databus rising clock from s7 to 0 and drives r/w high @ifdef bufena { equations bufena = (!cpu_nuds.pin # !cpu_nlds.pin) & mem_selected; } "// MUX switcher generator mux_switch_column_address.aclr = reset; mux_switch_column_address.clk = !clock; "clocked at falling edge of cpu/cpld clock mux_switch_column_address := access_ras.fb; "// set to 1 on negedge after beginning of access_ras (put out column address) //returns to 0 by access_ras gone 0 by async reset by as high after cpu clock going low to state s7, falling clock to state s1 -- x nS from clock low to s7 to as negated???? // DRAM MAx (daxx) multiplexor with refresh row count declarations "ras only refresh / row count not implemented rac11..rac0 node istype 'com'; equations [rac11..rac0] = [1,1, 1,1 ,1,1 ,1,1 ,1,1 ,1,1]; when !( (cpu_nas.pin=='0') & mem_selected ) then [da11..da0] = [rac11..rac0]; else when (mux_switch_column_address.fb == '1') then {da11=0; da10=0; [da9..da0] = [a10..a1].pin; } else [da11..da0] = [a22..a11].pin; "// cas before ras refresh cycle generator "CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 ns 17 "CAS hold time (CAS -before-RAS refresh) tCHR 10 10 ns "CAS to RAS precharge time tCRP 5 5 ns "121 Clock Low to AS, DS Negated — 62 — 50 — 40 — 40 3 30 3 25 ns rfsh_cas.clk = !clock; "neg. edge cpu clock (when as negated...) rfsh_cas.aclr = !cpu_nas.pin; " async reset when as asserted "could use delayed cpu_nas, 3 ns hold is little rfsh_cas := !rfsh_cas.fb & (cpu_nas.pin); "TOGGLES?? while no AS rfsh_ras = rfsh_cas.fb & clock; "// output signals generator ras = access_ras.fb # rfsh_ras; ucas = ((cpu_nuds.pin=='0') & access_cas.fb) # rfsh_cas.fb; lcas = ((cpu_nlds.pin=='0') & access_cas.fb) # rfsh_cas.fb; "Output buffer turn off delay time from OE tOEZ 3 - 13 ramoe = (cpu_r_w.pin == '1') & (!cpu_nuds.pin # !cpu_nlds.pin) & mem_selected ; ramwr = (cpu_r_w.pin == '0') & (!cpu_nuds.pin # !cpu_nlds.pin) & mem_selected ; "ramwr and data to ram must be valid by cas "// autoconfig data forming declarations "sets la = [a6.pin,a5.pin,a4.pin,a3.pin,a2.pin,a1.pin,.x.]; autodata15..autodata12 node istype 'com'; acdo = [autodata15..autodata12]; equations when (la==0) then acdo = [1,1,1,0]; else when (la==2) then @ifndef fourmeg {acdo = [0,0,0,0];} // 0000 for 8mb @ifdef fourmeg {acdo = [0,1,1,1];} // 0111 for 4mb else when (la==4) then acdo = ^hE; else when (la==6) then acdo = ^hE; else when (la==8) then acdo = 3; else when (la==^h0A) then acdo = ^hF; else when (la==^h10) then acdo = ^hE; else when (la==^h12) then acdo = ^hE; else when (la==^h14) then acdo = ^hE; else when (la==^h16) then acdo = ^hE; else when (la==^h40) then acdo = 0; else when (la==^h42) then acdo = 0; else acdo = [1,1,1,1]; // out autoconfig data (E8xxxx) declarations acdo_enable node istype 'com'; equations acdo_enable= (cpu_r_w.pin & !cpu_nuds.pin & ([a23..a16].pin == ^hE8) & autoconfig_started.fb & !autoconfig_done.fb); [d15..d12]=acdo; [d15..d12].oe=acdo_enable; // autoconfig cycle off -> on -> off autoconfig_started.clk = clock; autoconfig_started.aclr = reset; synch0.clk = clock; synch0.aclr = reset; synch1.clk = clock; synch1.aclr = reset; synch0 := !config_nin.pin; synch1 := synch0.fb; when (synch1.fb == '1') then autoconfig_started := '1'; else autoconfig_started := autoconfig_started.fb; "hold equations autoconfig_done.aclr = reset; autoconfig_done.clk = cpu_nas.pin; "rising edge clocks when (!cpu_r_w.pin & ([a23..a16].pin == ^hE8) & ([a6..a3].pin == [1,0,0,1]) & autoconfig_started.fb) // write at $E80048..$E8004E then autoconfig_done := '1'; else autoconfig_done := autoconfig_done.fb; "hold config_nout = !autoconfig_done.fb; "w,oe,ras,ucas,lcas "!as -> da='111... "0 as -> da=a21.. "as ->viive0ns -> ras "ras->viive10ns->da=lo "ras to cas 45 ns "da=lo ->0ns -> cas (u,l) "10 ns, "s0-s1:fc, ei w mutta r, ei a "s1-s2:a "s2-s3:as, write data (r,uds lds) "s3-s4:d "s4-s5:uds,lds (dtack) "s5-s6 "s6-s7 dataa sisaan, "s7-s0:ei as, ei uds, ei lds, ei d, data sisaan "s0-s1:ei a, ei w, fc "read modify write: tas, not on amiga END